library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity ffdc_fall is
port( CLK : in  std_logic;
	   RST : in  std_logic;
	   EN  : in  std_logic;
	   D   : in  std_logic;
	   Q   : out std_logic
);
end ffdc_fall;

architecture async of ffdc_fall is
begin

	pQ : process(CLK,RST)
		variable tmp_q : std_logic;
	begin
		if RST = '1' then
				tmp_q := '0';
		elsif falling_edge(CLK) then
			if EN = '1' then
				tmp_q := D;
			end if;
		end if;
		Q <= tmp_q;
	end process;
	
end async;
